1. Field of the Invention
The present invention relates to a non-volatile memory device and an inspection method for a non-volatile memory device.
2. Description of the Related Art
Flash memories and EEPROMs, (hereafter, simply called “memory cells”) are known as non-volatile memory devices. Data stored in the non-volatile memory is not deleted even if the power supply is turned off, provided that it is not erased or overwritten.
Data is written by means of channel hot electrons. Channel hot electrons are generated when a predetermined constant current flows between the source and drain of memory cell. FIG. 1 is a circuit diagram partly showing the structure of a conventional non-volatile memory device. This non-volatile memory device comprises a current supply circuit 106, a current supply circuit 107 (including a switch 124), a plurality of memory cells 1151, 1152 (although only two are illustrated in the drawing), a plurality of bit lines 117 (although only one is illustrated in the drawing), a plurality of word lines 1181, 1182 (although only two are illustrated in the drawing), and a plurality of source lines 119 (although only one is illustrated in the drawing). A memory cell array 112 is described as an example. In the memory cell array 112, memory cells 1151 and 1152 shares the source line 119.
The bit lines 117 extend in the Y direction (first direction) The word lines 1181, 1182 extend in the X direction (second direction) which is substantially perpendicular to the Y direction (first direction).
Memory cells 1151 and 1152 are disposed respectively at the positions where the plurality of bit lines 117 and the plurality of word lines 118 intersect with each other. In the memory cells 115, data is written by means of channel hot electrons. Channel hot electrons are generated when a predetermined constant current flows between the source and drain of memory cell 1151 and 1152. The non-volatile memory device illustrated in FIG. 1 is a split gate type non-volatile memory device. The control gate of this memory is connected to the word line 118, the source, to the source line 119, and the drain, to the bit line 117.
The current supply circuit 106 is able to supply a constant current, which is substantially uniform, to the memory cells 1151 and 1152 and its corresponding bit line 117. The current supply circuit 107 supplies a current to the bit line 117, via the switch 124.
The operation of writing data to this memory cell 1151 is described below.
Firstly, a selected bit line 117s, a selected word line 1181s and a selected source line 119s are selected respectively among the plurality of bit lines 117, the plurality of word lines 118 and the plurality of source lines. A selected cell 1151s is selected among the plurality of memory cells, by means of the selected bit line 117s and the selected word line 1181s. Next, a voltage VSW (source voltage) is applied to the selected source line 119s, a voltage VWW (gate voltage) is applied to the selected word line 1181s. The current supply circuit 106 supplies a predetermined constant current from the selected source line 119s to the selected bit line 117s via the source of the selected cell 1151s and the drain of the selected cell. In this case, the voltage VBW of the selected bit line (namely, the drain voltage), is VWW−Vth, where Vth is the threshold voltage of the selected memory cell 1151s. When the constant current flows in the selected memory cell 1151s, channel hot electrons are generated. Data is written to the memory cell 115s by injecting these channel hot electrons to the floating gate of the cell 1151s. 
The data is read out from the memory cell 115 as described below.
Firstly, a selected bit line 117s and a selected word line 1181s are selected respectively among the plurality of bit lines 117 and the plurality of word lines 118. The plurality of source lines 119 are fixed to 0V and are not selected. A selected cell 1151s is selected among the plurality of memory cells on the basis of the selected bit line 117s and the selected word line 1181s. Next, a voltage VWR (gate voltage) is applied to the selected word line 1181, and a voltage VBR (drain voltage) is applied to the selected bit line 117s. A sense amplifier (not illustrated) senses the current that flows in the path from the selected bit line 117s, to the drain of the selected cell 1151s, the source of the selected cell 1151s, and the corresponding source line 119s (0V). Since the current varies depending on the electric charge (stored data) accumulated in the floating gate, then it is therefore possible to read out the data.
When a write operation is performed in the memory cell 1151s described above, if the threshold voltage Vth is high, then the drain voltage of the memory cell 1151s (=voltage of bit line 117, VBW=VWW−Vth) becomes low. In this case, the difference between the source voltage of the memory cell 1152 (=voltage of source line 119, VSR=fixed value) and the drain voltage becomes high, and it becomes easier for channel hot electrons to be generated in the memory cell 1152. Thereby, non intentional writing (writing disturb) may be caused.
Therefore, it is desirable to screen a memory cell which has high threshold voltage Vth such as 1151s. It is required that the reliability of the memory cell is improved.
Related technology for a non-volatile memory device is disclosed in Japanese Patent No. 3198998.
This non-volatile memory device comprises a first and second voltage supply circuits. The first voltage supply circuits apply a first voltage to the non-selected memory cells. The second voltage supply circuits apply a second voltage to the selected memory cells. The timing of applying first voltage and second voltage is controlled.
Related technology for a non-volatile memory device is also disclosed in Japanese Unexamined Patent Application Publication No. 2004-14052.
This memory device is provided with a memory cell array in which memory cell units are arranged. In this memory device, a ground potential is given to a word line being adjacent to the word line to be written after a potential being larger than 0V is given, and a writing potential is given to the word line to be written.